1. Field of the Invention
This invention relates to computer arithmetic and, more particularly, to floating point multiplication hardware.
2. Description of the Related Art
Many general purpose microprocessors and other types of processors such as digital signal processors perform arithmetic computations, such as addition, subtraction, multiplication, and division. Often, such computations are performed on operands that are defined to be integer values. However, the numerical range of a given 2's complement integer of N bits is from −(2N) to 2N−1. This range may be insufficient for some applications, such as scientific modeling applications, which may need to manipulate real numbers across a wide numerical range.
To provide greater flexibility in representing real quantities, numerous floating point number formats have been defined. One such format, designated IEEE 754, defines a signed single-precision floating point value including 24 mantissa bits and 8 exponent bits, a signed double-precision floating point value including 53 mantissa bits and 11 exponent bits, and a signed extended-precision floating point value including 64 mantissa bits and 15 exponent bits. The IEEE 754 format enables representation of a much wider numerical range than a 2's complement integer format: for example, single precision range is approximately +/−2−126 to +/−2127 and double precision range is approximately +/−2−1022 to +/−21023.
While real number arithmetic using floating point number formats may be emulated by software performing integer computations, such emulation may be unacceptably slow for a given application. Therefore, many general purpose microprocessors and other processor types include hardware support for floating point number formats such as IEEE 754. Such support may include providing a floating point execution unit configured to perform operations such as multiplication, addition, and more complex numerical functions using floating point format operands. Processors including hardware floating point support may greatly improve the performance of applications programmed to use floating point data.
Floating point arithmetic performance improvement through hardware support may come at a substantial cost, however. In some implementations that use iterative floating point multiplications to approximate floating point division and transcendental functions, additional bits of precision may be added to the mantissa value for multiplication operations to ensue that the resulting division and transcendental functions have the desired level of precision. For example, to provide 64-bit precision of results for transcendental functions, it may be necessary to provide hardware support for 76-bit by 76-bit multiplication. However, hardware to support such a multiplication may require over five times the device count and die area of a 32-bit by 32-bit integer multiplier.
In addition to potentially increasing overall processor die size and therefore manufacturing costs, increased area due to floating point operation support may result in a substantial increase in total processor power consumption. As processor clock frequencies and power requirements continue to increase, chip packaging and system designs capable of supplying higher power demands and dissipating excess heat may become costlier. Therefore, careful management of chip power consumption through microarchitecture and design choices in floating point logic and other functional areas may become an increasingly important aspect of a successful processor design.